TapTechNews May 14 News, SK Hynix not only shared the expectation that the development cycle of HBM4E memory will be shortened to one year at the 2024 IEEE IMW International Storage Workshop, but also introduced more details of the memory.
SK Hynix technical staff Kim Kwi Wook stated that the company plans to use 1cnm process to build 32Gb DRAM wafers for HBM4E memory.
In fact, the three major memory manufacturers have not yet mass-produced DRAM wafers with 1cnm (the sixth generation 10+nm level) process.
TapTechNews previously reported that the first batch of 1cnm DRAM from Samsung Electronics and SK Hynix is expected to achieve mass production this year, while Micron will be slightly later, waiting until next year. The new generation of wafers is expected to bring improvements in density and energy efficiency.
Currently, SK Hynix uses 1bnm process DRAM wafers on HBM3E memory, and it has not been confirmed whether HBM4 will update the DRAM wafer process.
In a recent report, Korean media TheElec believes that SK Hynix has moved up the mass production time of HBM4 to the second half of 2025, so it is more in line with the development pace to continue using 1bnm wafers.
Current mainstream HBM3E products use 24Gb DRAM wafers, allowing HBM3E memory to achieve a single stack capacity of 24GB under 8 layers of stacking. If 12 layers of stacking are used, the HBM3E stack can reach 36GB.
With the update to 32Gb DRAM wafers in future HBM4E memory, the 12-layer stack version can achieve a single capacity of 48GB, and the 16-layer version can even reach a large scale of 64GB, creating more possibilities for AI use cases.
Kim Kwi Wook expects that HBM4E memory can improve bandwidth by 40%, density by 30%, and energy efficiency by 30% compared to HBM4.
When discussing the bonding technology route, the researcher mentioned that hybrid bonding still faces the issue of low yield, and it is unlikely that SK Hynix will adopt hybrid bonding in the next generation HBM4 products.