Samsung to Launch 4F2 VCT DRAM Prototype Next Year

TapTechNews May 21st news, comprehensively reported by South Korean media ZDNetKorea and TheElec, Samsung Electronics' Executive Vice President Lee Siwoo stated at the IEEE IMW 2024 seminar held this month that the company plans to launch a 4F2 VCT DRAM prototype next year. (TapTechNews note: Vertical Channel Transistor, Vertical Channel Transistor).

Currently, in the field of 3D DRAM commercial research focuses on two structures:

One is 4F2 VCT (Vertical Channel Transistor) DRAM; the other is VS-CAT (Vertical Stacked-Cell Array Transistor, Vertical Stacked Cell Array Transistor) DRAM.

The former mainly develops in the z-direction in the DRAM cell structure, while the latter is to stack multiple layers of DRAM similar to 3D NAND.

The existing DRAM memory on the market adopts a 6F2 structure. Switching to a 4F2 structure can reduce the area by about 30% and increase the storage density, but it also puts higher requirements on DRAM materials.

In addition to increasing capacity through stacking, VS-CAT DRAM can also reduce current interference. Samsung Electronics expects that it will adopt a dual-wafer structure with separated memory cells and peripheral logic cells, because continuing the traditional single-wafer design will bring a serious area overhead.

After the production of the memory cell wafer and the logic cell wafer is completed respectively, wafer-to-wafer (W2W) hybrid bonding is required to obtain the VS-CAT DRAM finished product. This process is similar to the Xtacking technology used by Yangtze Memory in 3D flash memory.

Currently, Samsung Electronics has achieved a 16-layer stacked VS-CAT DRAM internally, while Micron is at the 8-layer stacked level.

Samsung Electronics also discussed the possibility of using the BSPDN backside power supply technology for 3D DRAM memory at the meeting. Lee Siwoo believes that this technology is helpful for fine power supply regulation of individual memory banks in the future.