AMD's Lisa Su Wins imec Innovation Award, Sets Goals for Energy Efficiency

TapTechNews May 24th news, at the ITF World 2024 conference held by the Interuniversity Microelectronics Research Center (IMEC) in Belgium, AMD's chief executive officer, Lisa Su, won the imec Innovation Award, acknowledging her innovative capabilities and industry leadership.

After receiving the award, Lisa Su began to introduce the company's 30x25 goal, that is, to increase the energy efficiency of computing nodes by 30 times by 2025. Lisa Su also predicted that a method to find a 100-times improvement in energy efficiency could be found between 2026 and 2027.

Due to the explosive development of generative artificial intelligence LLMs such as ChatGPT, concerns about the power consumption of artificial intelligence have become a focus of attention, but AMD had the foresight to anticipate the power consumption problem of AI applications as early as 2021.

AMD thus set the 30x25 goal to improve the energy efficiency of data center computing nodes and specifically pointed out that the energy consumption of AI and HPC is an imminent problem.

TapTechNews learned from the report that AMD set its first ambitious energy goal as early as 2014, the pioneering 25x20 goal, that is, to increase the energy efficiency of consumer processors by 25 times by 2020, and AMD has exceeded this goal by increasing it by 31.7 times.

As the computing power required for training models increases, the problem will only get worse. Su pointed out that the scale of the first image and speech recognit ion artificial intelligence model used to double every two years in the past, which is basically in line with the progress rate of computing power in the past decade.

And now, the scale of generative artificial intelligence models is growing at a rate of 20 times per year, exceeding the rate of progress of computing and memory.

Lisa Su believes that currently the largest model is trained on tens of thousands of GPUs and consumes as much as tens of thousands of megawatts of electricity, and the rapidly expanding model scale may soon require hundreds of thousands of GPUs for training, and perhaps training a single model will require several thousand megawatts of power.

AMD has adopted a multi-pronged strategy to improve energy efficiency, including a wide range of methods from silicon architecture and advanced packaging strategies to artificial intelligence dedicated architectures, systems and data center-level adjustments, as well as software and hardware collaborative design plans.

Lisa Su said that the next step in AMD's silicon technology roadmap is the 3-nanometer fully gate-all-around (GAA) transistor aiming to improve energy efficiency and performance while continuing to focus on advanced packaging and interconnect technologies to achieve more energy-efficient and cost-effective modular designs.

Advanced packaging plays a key role in expanding the design scale, which can generate more horsepower within the limitations of a single chip package. AMD has adopted 2.5D and 3D hybrid packaging to maximize the computing power per watt of d ata center silicon per square millimeter.