SK Hynix Considers Shifting to 4F2 or 3D DRAM to Cut Costs

TapTechNews August 13th news, according to the Korean media THEELEC report, SK Hynix researcher Seo Jae-Wook said at the academic conference held in Suwon, South Korea on the 12th local time that in the future, it is considering turning to DRAM memory with 4F2 or 3D structure to reduce cost pressure.

Seo Jae-Wook stated:

Since 1c DRAM, the cost of EUV lithography has increased rapidly, and now it is time to consider whether it is profitable to manufacture DRAM in this way.

(SK Hynix) is also considering whether to switch to VG (TapTechNews note: that is, Vertical Gate) or 3D DRAM from the next-generation product.

Seo Jae-Wook mentioned here that VG DRAM is 4F2 DRAM, and Samsung Electronics calls it VCT (Vertical Channel Transistor) DRAM, which is a new type of memory with a vertically constructed unit structure.

The source, gate, drain and capacitor of 4F2 DRAM are placed from bottom to top, and the word line and bit line are respectively connected to the gate and source. Compared with the existing 6F2 DRAM, the chip area can be reduced by about 30%. Seo Jae-Wook predicts that VG DRAM will be mass-produced after the 0anm node.

Samsung Electronics, SK Hynix, and Micron's 1cnm DRAM using EUV lithography is about to be launched in 2024-2025. And starting from the next-generation 1dnm node, advanced memory will use EUV multiple exposures, greatly increasing the cost of the EUV lithography link in the production process.

Seo Jae-Wook said that by using the VG or 3D DRAM structure, the EUV lithography cost of memory can be reduced to less than half of the traditional 6F2 DRAM.

Among them, for VG DRAM, the low lithography cost can be maintained for another 1-2 generations of processes, but after that the EUV cost will return to the steep upward trajectory; while the 3D DRAM route requires large-scale investment in deposition and etching equipment.