TSMC Proposes Advanced Backside Supply Power Network Solution
TapTechNews July 4 news, according to the Commercial Times report, TSMC has proposed a more complete Backside Supply Power Distribution Network (BSPDN) solution. The adopted method is the most direct and efficient, but the cost is complex and expensive production.
Why Backside Supply Power Distribution Network?
As transistors get smaller and smaller, the density gets higher and higher, and the number of stacking layers also increases. Therefore, in order to power transistors and transmit data signals, it is necessary to pass through 10-20 layers of stacking, greatly increasing the complexity of the circuit design.
The Backside Supply Power Technology (BSPDN) directly transfers the power supply network originally arranged together with the transistors to the backside of the transistors and rearranges it, which is also an innovation in the three-dimensional structure of the transistors.
This technology can increase the density of transistors per unit area while avoiding signal interference between transistors and the power supply network, reducing wiring congestion at the back end of the line and providing power performance advantages and enhancing the reliability of the chip.
Technical Difficulties
The difficulty of backside supply power is that the backside of the wafer needs to be polished until it is nearly in contact with the transistor, but at the same time, this will greatly reduce the rigidity of the wafer. Therefore, a carrier wafer must be bonded to the front side of the wafer to carry the manufacturing process on the backside.
In addition, in the nTSV (nano-through silicon via) process, in order to ensure uniform copper metal coating in the nano-scale holes, more equipment is also needed to assist in detection.
TSMC's more direct and efficient
TapTechNews checked the public data. There are currently 3 solutions for the global backside supply power network technology:
Intel's PowerVia
Imec's BuriedPowerRail in Belgium
TSMC's SuperPowerRail
A transistor is composed of four main components, including the source, the drain, the channel and the gate. The source is the entrance where the current flows into the transistor, and the drain is the exit; the channel and the gate are responsible for coordinating the movement of electrons in sequence.
TSMC's power transmission line in the A16-node process technology is directly connected to the source and the drain, so it is more complex than Intel's backside supply power technology. TSMC said that the reason for its decision to adopt a more complex design is to help improve the performance of the customer's chips.
TSMC said that under the same operating voltage (Vdd), the A16-node using SuperPowerRail has an operation speed 8-10% faster than N2P; under the same operation speed, the power consumption is reduced by 15%-20%, and the chip density is increased by up to 1.10 times.
The method adopted by TSMC is the most direct and effective, but the cost is complex and expensive production. To reflect the value, TSMC has also made adjustments in the price. It is reported that the advanced process part has been successfully increased in price and will start to increase in price in January next year, especially for the 3nm/5nm AI product line, with an adjustment of 5% to 10%.