TSMC Showcases Advanced HBM4 Base Dies at 2024 European Technology Symposium

TapTechNews reported on May 17th that TSMC recently attended the 2024 European Technology Symposium, showcasing the HBM4 base Dies manufactured using 12FFC+ (12-nanometer level) and N5 (5-nanometer level) process technologies to enhance the performance and efficiency of HBM4.

The translation of TSMC's Design and Technology Platform Senior Director is as follows:

We are collaborating with major HBM memory partners (Micron, Samsung, SKhynix) to achieve HBM4 full stack integration on advanced nodes. The 12FFC+ base Dies offer cost advantages while meeting HBM performance requirements, and the N5 base Dies can achieve the expected speed of HBM4 with lower power consumption.

The base chips manufactured using TSMC's 12FFC+ process (derived from the company's mature 16-nanometer FinFET technology) will enable the construction of 12-Hi and 16-Hi HBM4 memory stacks with capacities of 48GB and 64GB, respectively.

The use of the 12FFC+ process will enable cost-effective base chips that will use silicon interposers to connect memory to the host processor.