Samsung Electronics' BSPDN Technology and Future Process Roadmap

TapTechNews August 23rd news, comprehensively reported by Korean media TheElec and Hankyung, LeeSun-Jae, the senior vice president of the wafer foundry PDK development team of Samsung Electronics, introduced the benefit situation of the BSPDN backside power supply network technology at the Siemens EDA Forum 2024 in Seoul yesterday.

LeeSun-Jae said that compared to the 2nm process using the traditional FSPDN power supply method, the SF2Z node using BSPDN can significantly improve the circuit voltage drop problem. Specifically in terms of data, it can reduce the chip area by about 17%, increase the energy efficiency by about 15%, and enhance the performance by about 8%.

Referring to TapTechNews' previous report, Samsung Electronics announced the latest advanced process roadmap at the Samsung Foundry Forum 2024 North America: the initial version of the 2nm process SF2 is scheduled to be mass-produced in 2025, the improved version SF2P is in 2026, and the SF2Z will be mass-produced in 2027.

For SF2P, LeeSun-Jae said that Samsung Electronics plans to achieve a 12% performance improvement, a 25% power consumption reduction, and an 8% area reduction compared to the SF2 process.