SK Hynix to Build HBM4 Memory with TSMC's N5 Process Base Die
TapTechNews July 17th news, the Korean Economic Daily (Hankyung) stated that SK Hynix will use the base die of TSMC's N5 process version to build HBM4 memory.
The JEDEC standard for the new generation of HBM memory, HBM4, is about to be finalized. And according to TapTechNews' previous report, SK Hynix's first batch of HBM4 products (12-layer stacked version) is expected to be launched in the second half of 2025.
SK Hynix and TSMC signed a memorandum of understanding for cooperation in April this year and announced that they will strengthen cooperation on the base die of HBM memory.
And at the 2024 Technology Symposium in Europe, TSMC said that the company has prepared two HBM4 memory base dies, namely the N12FFC+ version for price-sensitive products and the N5 version for high-performance applications.
Among them, the area of the N5 version base die is only 39% of that of the N12FFC+ version, and the logic circuit frequency can reach 155% of that of the N12FFC+ version at the same power, and the power consumption at the same frequency is only 35%.
The N5 process version base die can achieve an interconnect pitch of 6 to 9 μm level, and can also support 3D vertical integration of HBM4 memory with the logic processor in addition to the currently popular 2.5D packaging integration. This vertical structure can provide greater memory bandwidth and will profoundly change the HPC & AI chip ecosystem.
The transfer of HBM memory base die to logic wafer fabs for production is also the best proof of the convergence of the two major fields of semiconductor manufacturing. Korean media mentioned in the report that both SK Hynix and Samsung Electronics are supplementing logical design talents for their HBM memory teams.
Related reading:
News said that Samsung Electronics uses its own 4nm advanced process to build HBM4 memory logic chips