AlphawaveSemi Develops First 3-nanometer UCIe Chiplet for Advanced Packaging

TapTechNews August 1st news, AlphawaveSemi has newly developed the industry's first 3-nanometer UCIe chiplet, realizing die-to-die connections for system-in-packages (SiP) using TSMC's CoWoS packaging technology.

This chiplet group is aimed at high-demand areas such as hyperscale, high-performance computing, and artificial intelligence, allowing users to build various system-in-packages.

AlphawaveSemi's senior vice president and general manager of custom silicon and IP, Mohit Gupta, said:

Successfully launching the 3-nanometer 24 Gbps UCIe subsystem with TSMC's advanced packaging is an important milestone for AlphawaveSemi, demonstrating the company's top-notch connectivity solution expertise in leveraging TSMC's 3D Fabric ecosystem.

The 3-nanometer chiplet can also be used alone to connect chiplets that comply with the UCIe 1.1 standard, but the main purpose of this IP is to be integrated into other chiplets to enable die-to-die connections for AlphawaveSemi (for its customers) or companies that obtain IP licenses.

Silicon-verified 3-nanometer die-to-die interface IP is of great significance to the market, as it can build multi-chip SiP using TSMC's most advanced manufacturing process to date.

This 3-nanometer chiplet supports a bandwidth density of 8 Tbps/mm, uses TSMC's CoWoS 2.5D silicon-interposer-based packaging, and includes physical layer and controller IP, supporting various protocols such as PCIe, CXL, AXI-4, AXI-S, CXS, and CHI.

AlphawaveSemi's UCIe subsystem IP complies with the latest UCIe specification Rev1.1 and is equipped with extensive testing and debugging functions, including JTAG, BIST, DFT, and KnownGoodDie (KGD) functions.

TapTechNews briefly introduces the relevant proprietary terms involved in this article:

Die: A die is an unpackaged small piece of an integrated circuit body made of semiconductor material, and the established function of this integrated circuit is realized on this small piece of semiconductor.

Chiplet: A chiplet is a miniature integrated circuit that contains a well-defined subset of functions. It is designed to be combined with other small chips on a single package interposer. A set of chiplets can be implemented in a mix-and-match Lego-style stacked components.

UCIe: Standing for Universal Chiplet Interconnect Express, it is an open specification suitable for die interconnects and serial buses between chiplets.

CoWoS: It can be divided into CoW and WoS: CoW (Chip-on-Wafer) is chip stacking; WoS (Wafer-on-Substrate) is stacking chips on the substrate.

System-in-Package: A concept of integrated circuit packaging, which is to configure all or most of the electronic functions of a system or subsystem in an integrated substrate, and the chips are packaged in a 2D or 3D way to bond to the integrated substrate.