TapTechNews July 16, MoneyDJ reported yesterday (July 15) that TSMC has formed a dedicated team to explore a new packaging solution of fan-out panel-level packaging (FOPLP) and plans to build a small pilot production line (miniline) to advance the goal of replacing 'round' with'square'.
TSMC started to develop the FOWLP (fan-out wafer-level packaging) technology named InFO (Integrated Fan-Out Packaging) in 2016 and used it on the A10 chip of the iPhone 7 series mobile phones. Later, packaging and testing factories actively promoted the FOWLP solution, hoping to attract customers with lower production costs.
However, at this stage, the FOWLP packaging solution has not made significant breakthroughs in technology and still remains on mature process products such as PMIC (Power Management IC) in terms of terminal applications.
And the latest news says that TSMC has this time formed a professional R & D team and plans to develop a rectangular semiconductor substrate with a length of 515 millimeters and a width of 510 millimeters, transferring advanced packaging technology from the wafer level to the panel level.
TapTechNews quoted sources as reporting that the FOPLP developed by TSMC can be regarded as a rectangular InFO, with the advantages of low unit cost and large-size packaging. In technology, it can further integrate other technologies on TSMC's 3Dfabric platform to develop 2.5D/3D and other advanced packaging to provide high-end product application services.
The FOPLP of TSMC can be imagined as a rectangular CoWoS. Currently, the product is targeted at the AIGPU field, and the main customer is NVIDIA. If this project progresses smoothly, it will debut as early as 2026-2027.
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