Belgian imec and ASML Make Breakthroughs in HighNA EUV Lithography for Logic and DRAM

TapTechNews August 8th news, the Belgian research center for microelectronics imec announced yesterday local time that in its HighNA EUV lithography laboratory in cooperation with ASML, it has successfully exposed the pattern structures of logic and DRAM for the first time using the HighNA EUV lithography machine.

In terms of the logic pattern, imec successfully patterned a single-exposure random logic structure, achieving a 9.5nm dense metal line (TapTechNews note: corresponding to 19nm Pitch), reducing the end-to-end spacing dimension to less than 20nm:

Not only that, imec achieved a random via with a center spacing of 30nm, showing excellent pattern fidelity and critical dimension consistency:

In addition, imec built a two-dimensional feature with a P22nm spacing through the HighNA EUV lithography structure, showing the potential of the new-generation lithography technology in two-dimensional wiring:

In the DRAM field, imec successfully patterned the DRAM design integrating the SNLP (StorageNodeLandingPad) and the bit line periphery with a single exposure, showing the ability of HighNA EUV to reduce the number of exposures:

The president and CEO of imec, Luc Vandenhove, said:

These results confirm the resolution capability that HighNA EUV lithography technology has long predicted, enabling metal layers with a spacing of less than 20nm with a single exposure.

Therefore, HighNA EUV will play an important role in the size expansion of logic and memory technologies, and this is one of the key pillars to push the roadmap into the 'angstrom era'.

These early demonstrations were made possible thanks to the establishment of the ASML-imec joint laboratory, which enables our partners to accelerate the introduction of HighNA lithography technology into the manufacturing field.