On May 16, TapTechNews reported that Japanese advanced wafer foundry company Rapidus signed a memorandum of understanding with US RISC-V architecture chip design company Esperanto to cooperate in developing low-power AI chips for data center applications.
Esperanto is a company specializing in large-scale parallel, high-performance, and energy-efficient computing solutions. They have previously released a RISC-V architecture multi-core AI/HPC accelerator chip called the ET-SOC-1.
This chip is built on TSMC's 7nm process and features 1088 64-bit low-power ET-Minion cores and 4 high-performance out-of-order ET-Maxion cores for OS support. The ET-SOC-1 chip also includes 160MB of on-chip SRAM cache.
TapTechNews previously reported that Rapidus had signed a 2nm AI accelerator collaboration agreement with another RISC-VAI chip design company, Tenstorrent, earlier this year.
At a press conference yesterday, Rapidus President Atsuyoshi Koike emphasized that the cooperation with Esperanto is in a different field from the previous agreement, targeting the increasingly urgent issue of power consumption:
According to a report from the International Energy Agency, driven by generative AI and other factors, the global data center electricity consumption may reach 1000TWh by 2026, equivalent to the electricity consumption of the entire country of Japan.
The collaboration between Rapidus and Esperanto will leverage their strengths in advanced processes and energy-efficient chip design to develop low-power data center compute chips fit for the AI era.