AMD's Future Zen5 and Zen6 Core Architectures

TapTechNews May 20th news, based on the information shared by the message sources Kepler_L2 and InstLatX64 in yesterday's tweet, each CCD of the AMD Zen6 processor can be equipped with up to 32 cores.

 AMDs Future Zen5 and Zen6 Core Architectures_0

Zen5

The current leaked information shows that AMD will officially announce the Zen5 core architecture in the Computex event to be held in June this year, and the first batch of products is expected to be on the shelves in the third quarter of 2024.

The AMD Zen5 and Zen5C cores are expected to be smaller than the existing Zen4 cores, which provides space for integrating more CCDs on the CPU package.

In the top-level EPYC chips, Zen4 deploys up to 12 CCDs, while Zen4C has up to 8 CCDs, the latter has two CCXs, each with 8 cores, and a maximum of 128 cores.

But in the next-generation products, AMD will stack up to 16 CCDs in the Zen5 architecture and 12 CCDs in the Zen5C architecture. Zen5 will retain the same single CCX design in the CCD, with a total of 8 cores and a maximum of 128 cores.

 AMDs Future Zen5 and Zen6 Core Architectures_1

And the Zen5C chip will adopt a single CCX, with a total of 16 cores and a maximum of 192 cores. TapTechNews attached the detailed comparison between the next-generation Zen5 and Zen5C with Zen4 and Zen4C chips:

CCDNumber of cores per CCDNumber of CCX in each CCDMaximum number of coresZen5C12161192Zen4C8162128Zen51681128Zen4128196

Zen6

It is reported that the AMD Zen6 core architecture will have three configurations: including 8 cores per CCD, 16 cores per CCD, and up to 32 cores per CCD.

If there are 16 cores in each CCD, then up to 32 cores can be obtained on dual-CCD components such as Ryzen CPUs, or up to 64 cores can be achieved using the same CCD layout.

 AMDs Future Zen5 and Zen6 Core Architectures_2

However, the chip with the highest number of cores is likely to be based on the Zen6C architecture, while AMD tends to use the standard Non-C chip on its high-end components.

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