Hunan University's Breakthrough in Low-Temperature 3D Chip Integration

TapTechNews May 25th news, on May 23rd, Hunan University released an announcement declaring that the team led by Professor Liu Yuan from the School of Physics and Microelectronics Science has developed a low-temperature van der Waals single-chip three-dimensional integration process. Related achievements were published in 'Nature'.

Related Background Introduction

Three-dimensional integration is a device system that stacks multiple independent chips or functional layers in the vertical direction, enabling the vertical integration and collaborative work of functions such as logic, storage, and sensing, and it is an important technical route in the post-Moore era.

Currently, the commercial three-dimensional integration is mainly through packaging technology to vertically stack and interconnect multiple chips or multi-die. Single-chip three-dimensional integration is to directly vertically integrate multiple device layers within the same chip, and by directly fabricating each device layer on top of another device layer, it can further improve the interconnection density and performance of the chip.

Silicon-based single-chip three-dimensional integration faces a serious thermal budget problem, and the silicon channel fabrication process in the upper layer will lead to dopant diffusion and performance degradation of the underlying silicon devices, limiting the development of three-dimensional integration.

Team's Solution

In this process, the source/drain/gate electrodes, intra-layer interconnect metals, high-κ gate dielectrics, low-κ inter-layer dielectric layers, and inter-layer vertical vias and other circuit functional layers are first pre-fabricated on the sacrificial wafer, and then van der Waals integrated onto the semiconductor wafer at a low temperature of 120°C.

By layer-by-layer integrating the van der Waals pre-fabricated circuit layers and the semiconductor layer, the team achieved a 10-layer all-van der Waals single-chip three-dimensional system.

Advantages of This Process

This integration process does not have an impact on the electrical performance of the bottom molybdenum disulfide transistor, can ensure the intrinsic performance of the transistor, and realizes the three-dimensional heterogeneous integration and collaborative work of logic, sensing, and storage interconnection.

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