TapTechNews on June 20, citing Nikkei Asia, reported that TSMC is researching a new advanced chip packaging method, using a rectangular substrate instead of the traditional circular wafer, thereby placing more chips on each wafer.
Insiders revealed that the rectangular substrate is currently in the experimental stage, sized 510mm by 515mm, with an available area that is more than three times that of a circular wafer, and adopting a rectangle means less unused area remaining at the edges.
It is reported that this research is still in the early stages, and coating photoresist in the tip chip packaging on the new-shaped substrate is one of the bottlenecks, and it requires a chipmaker with deep financial resources like TSMC to push equipment manufacturers to change the equipment design.
In chip manufacturing, chip packaging technology was once considered to have relatively low technical content, but it is becoming increasingly important in maintaining the speed of semiconductor progress. For AI computing chips like NVIDIA H200 or B200, simply using the most advanced chip production technology is not enough.
Take the B200 chipset as an example. TSMC's pioneering advanced chip packaging technology, CoWoS, can combine two Blackwell graphics processing units together and connect with eight high-bandwidth memories (HBM) to achieve rapid data throughput and accelerated computing performance.
TSMC's advanced chip stacking and assembly technology used for manufacturing AI chips for NVIDIA, AMD, Amazon, and Google uses 12-inch silicon wafers, which are the largest wafers currently. As the size of chips increases, 12-inch wafers are gradually becoming insufficient.
Insiders said that only 16 sets of B200 can be manufactured on one 12-inch wafer, and this is still under the condition of 100% production yield. According to Morgan Stanley's estimate, older H200 and H100 chips can be packaged about 29 sets on one wafer.