Rapidus and IBM to Collaborate on 2nm Chiplet Packaging Technology

TapTechNews, June 12 - Rapidus, an advanced foundry in Japan, announced earlier this month that it will expand its cooperation with IBM in the 2-nanometer process field from the front end to the back end, and jointly develop advanced packaging and mass production technology of Chiplet.

According to the agreement signed by both parties, engineers from IBM and Rapidus will cooperate in IBM's North American factory to develop advanced semiconductor packaging technology for HPC systems. In the future, Rapidus will apply these technologies to commercial foundry production.

Rapidus has previously received a special subsidy of 53.5 billion yen (TapTechNews note: currently about 2.473 billion yuan) for the back-end process from the Japanese Ministry of Economy, Trade and Industry, and plans to rent the vacant plant of Seiko Epson adjacent to its IIL-1 wafer fab to build advanced packaging capacity supporting the 2-nanometer process.

The president and CEO of Rapidus, Atsuyoshi Koike, said:

After jointly developing 2-nanometer semiconductors, we are very pleased to officially announce today that we have reached a cooperation with IBM on establishing chip packaging technology.

We will make full use of this international cooperation to ensure that Japan plays a more important role in the semiconductor packaging supply chain than it does now.

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