Applied Materials Announces Innovative Chip Wiring Technology with Ruthenium

TapTechNews July 10th news, Applied Materials, Inc. released a press release on July 8th, announcing the launch of an innovative chip wiring technology. By using ruthenium for the first time in mass production in the industry, it enables the expansion of copper chip wiring to the 2-nanometer node and higher levels, and the resistance is reduced by up to 25% at most.

TapTechNews attached the relevant video introduction as follows:

At present, the transistor scale of the current chip has developed to the level of tens of billions. Fine copper wires need to be used for connection in the production process, and the total length may exceed 95.5 kilometers (about 60 miles).

The existing mainstream chip wiring usually starts from a layer of dielectric material film. After the etching process, a channel that can fill copper thin wires is formed.

In the past decades of development, the main wiring combination in the industry has adopted a low dielectric constant film and copper. Each layer of the low dielectric constant film is etched to form a trench, and then a barrier layer is deposited to prevent copper from migrating into the chip and causing yield problems.

Then, a liner is coated on the barrier layer to ensure the adhesion in the final copper reflow deposition process, so as to slowly fill the remaining volume with copper, and then continuously iterate and improve miniaturization, performance and power consumption, etc.

Applied Materials' newly proposed enhanced BlackDiamond is the latest product of the existing BlackDiamond PECVD (Plasma Enhanced Chemical Vapor Deposition) series.

This new material reduces the smallest k value, miniaturizes to 2 nanometers and below, and at the same time provides higher mechanical structural strength, which is crucial for chip manufacturers and system companies that will upgrade 3D logic and memory stacks to new heights.

Applied Materials' latest Integrated Materials Solution (IMS), which combines six different technologies in a high vacuum system, including the industry's first material combination, allows chip manufacturers to miniaturize copper wiring to the 2-nanometer node and below.

The solution uses a bimetallic combination of ruthenium and cobalt (RuCo), reducing the liner thickness by 33% to 2 nm, generating better surface characteristics for void-free copper reflow, and in addition, the line resistance is reduced by up to 25%, thereby improving chip performance and power consumption.

The new Applied Endura Copper Barrier Seed IMS using Volta Ruthenium CVD (Chemical Vapor Deposition) technology has been adopted by all leading logic chip manufacturers and has begun shipping to customers at the 3-nanometer node.