TapTechNews on June 17, it was reported by Taiwanese media, the Commercial Times, that under the circumstance of tight capacity and high demand, TSMC will carry out price hikes for its 3/5nm advanced process and advanced packaging.
Among them, the 3nm foundry part will increase by more than 5%, and the advanced packaging quotation for the 2025 fiscal year will also increase by 10% to 20%.
In the 3nm process, almost all advanced chip design enterprises have placed orders with TSMC. The overall capacity utilization rate of TSMC's 3nm is close to full capacity for a long time and this trend will continue until 2025 and even 2026.
TSMC's 5nm family node also continues to receive AI semiconductor orders, and the capacity utilization rate is also relatively high.
In the field of advanced packaging, the capacity gap is mainly concentrated on the CoWoS process that realizes the integration of HBM memory and AI accelerators.
TSMC's CoWoS capacity in 2025 will reach 530,000 wafers, which is about 42,000 wafers per month on average, an increase from the current 33,000 wafers, but still less than the market demand of 600,000 wafers for the whole year.
TapTechNews noticed that, different from mobile chips, AI accelerators are mainly concentrated on sub-advanced nodes. For example, Nvidia's Blackwell GPU still uses the 4NP process based on TSMC's 5nm family.
However, for AI accelerators, CoWoS and its similar advanced packaging processes are essential. Whoever can get more advanced packaging capacity from TSMC can gain greater control and say in the AI accelerator market.
In this situation, Nvidia, the largest customer in this field of TSMC and currently occupying about half of the capacity, agreed to give some profit margin to TSMC in order to obtain more advanced packaging capacity and widen the output gap from the competitors.